The present invention concerns a method for determining the adjustment of a timepiece provided with an oscillator and an adjustment unit for the division rate of its frequency divider. It further concerns a timepiece arranged and adapted for application of the foregoing method.
Initially, it will be recalled that certain existing timepieces utilize, in order to adjust the frequency of their quartz oscillator which may be relatively stable but imprecise, an adjustment unit for the division rate of their divider chain which may be substituted for a trimmer utilized hitherto during numerous years. This substitution has brought about a certain progress by diminishing the energy consumption and the manufacturing price and through an improvement of the stability of operation. Examples of this technique are given in various invention publications. U.S. Pat. No. 3,895,486 describes an adjustment unit intended to inhibit a certain number of pulses among those supplied by the oscillator during a predetermined period. In this case the real frequency of the oscillator is chosen to be higher than its normal frequency. U.S. Pat. No. 3,777,471 describes an analogous system where the adjustment unit adds a certain number of pulses to those supplied by the oscillator, which the real frequency is in such case chosen to be lower than the normal frequency. In one or the other of these systems the adjustment unit is associated with a memory for which the state represents the magnitude of the adjustment to be realized.
The memory just mentioned may take the form of switches as in the case of the cited U.S. Pat. No. 3,895,486 or on the other hand may be formed of alterable electronic elements such as described in the U.S. Pat. No. 3,914,706. In either case, said memory stores in a coded form the information determining the division rate.
This being the case, the question arises to determine the running of the timepiece in order to introduce, during the manufacture for instance, the coded information necessary for the desired precision and good operation. The same question is posed to the watchmaker repairman who must be in a position to regulate the operation of a watch which either advances or retards. In order to do this, generally there is available apparatus permitting the detection of a signal emitted by the display system of the watch or of counters installed in the manufacturing assembly line in order to measure directly the signal present at the output of the frequency divider.
However, as the timepiece under consideration is provided with an adjustment unit intended to inhibit or to add a certain number of pulses during a predetermined period or adjustment cycle, the measurement of operation may take far too much time. Effectively, the correction signal which is introduced into the divider chain to modify the rate of division thereof is essentially aperiodic and it is necessary to await the end of a regulating period in order to obtain a correct measurement of the average running of the timepiece. In an example which will be described further on and for which the precision to be obtained is in the order of 3 ppm, it will be seen that this period may require up to 10 seconds, which period is incompatible with mass production of large series.
Various solutions have been proposed in order to overcome the difficulty and to shorten the measurement time. Thus, as shown in French patent publication No. 2 442 467 there is shown a logic circuit arranged to generate a measurement signal comprising pulses of which the distribution represents the division rate and the frequency of the oscillator. In this arrangement the operation of the timepiece is accelerated and one measures the period P of a noncorrected pulse train and the number N of pulses which are suppressed during this period (or, in other terms, the state of the memory). From this may be deduced by calculation the effect produced on the running of the timepiece. The British patent publication No. 2 043 967 describes a system of inspection of the state of a memory formed of switches. When a switch is operated, the display is driven at an accelerated speed which represents the contents of the memory.
The previously mentioned solutions present at least two difficulties. Initially, they resolve only a portion of the problem as posed. Effectively, if the two proposed methods are well adapted to provide a rapid inspection of the state to which the memory is regulated, on the other hand one knows nothing of the result or the effect which this may have on the state of the real running of the timepiece. This is due to the fact that in order to effect this inspection, the regulation exerted by the memory on the divider chain is suppressed. One is thus obliged to assume that, because the memory is to be found in a suitable state, the operation of the timepiece will be correct once the regulation has been re-established. However, nothing proves that for instance the inhibition circuit is functioning correctly, this being an absolute condition to obtain a good running of the timepiece as would be the case if the measurement was made with the circuit functioning. Following this, the proposed solutions will require special circuits to be added to the ordinary timekeeping circuits as well as a special control, these circuits and control being used only rarely whenever it is a matter of inspecting the running.
This invention proposes to overcome the aforesaid difficulties thanks to a method and a special timepiece executed in order to apply such method such as is hereafter defined in the claims.